View PALCE600_764633.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

USE GAL DEVICES FOR NEW DESIGNS
FINAL COM'L: H-15/25
CONNECTION DIAGRAMS Top View SKINNYDIP
I/O9
PLCC/LCC
CLK1 VCC I I I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I CLK2
12950G-2
VCC
EE CMOS High Performance Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
s Lattice/Vantis Programmable Array Logic (PAL) architecture s Electrically-erasable CMOS technology providing half power (90 mA ICC) at high speed -- -15 = 15-ns tPD -- -25 = 25-ns tPD s Sixteen macrocells with configurable I/O architecture s Registered or combinatorial operation s Registers programmable as D, T, J-K, or S-R s Asynchronous clocking via product term or bank register clocking from external pins s Register preload for testability s Power-up reset for initialization s Space-saving 24-pin SKINNYDIP and 28-pin PLCC packages s Fully tested for 100% programming yield and high reliability s Extensive third-party software and programmer support through FusionPLD partners
I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 I GND
3 4 5 6 7 8 9 10 11 12
22 21 20 19 18 17 16 15 14 13
4 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 NC 5 6 7 8 9 10 11
3
2
1 28 27 26 25 24 23 22 21 20 19 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 NC
12 13 14 15 16 17 18 I/O16 I CLK2 GND GND I/O8
12950G-3
GENERAL DESCRIPTION
The PALCE610 is a general purpose PAL device and is functionally and fuse map equivalent to the EP610. It can accommodate logic functions with up to 20 inputs and 16 outputs. There are 16 I/O macrocells that can be individually configured to the user's specifications. The macrocells can be configured as either registered or combinatorial. The registers can be configured as D, T, J-K, or S-R flip-flops. The PALCE610 uses the familiar sum-of-products logic with programmable-AND and fixed-OR structure. Eight product terms are brought to each macrocell to provide logic implementations. The PALCE610 is manufactured using advanced CMOS EE technology providing low power consumption. Moreover, it is a high-speed device having a worstcase tPD of 15 ns. Space-saving 24-pin SKINNYDIP and 28-pin PLCC packages are offered. This device can be quickly erased and reprogrammed providing for easy prototyping. Once a device is programmed the security bit can be used to provide protection from copying a proprietary design.
Note: Pin 1 is marked for orientation
PIN DESIGNATIONS
CLK GND I I/O NC VCC = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage
BLOCK DIAGRAM
I I/O16 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 CLK1
4
28
28
28 28 28 Programmable AND Array 40 x 160 28 28 28
28
28
28
28
28
28
28
28
CLK2
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
12950G-1
Amendment /0
2-374
Publication# 12950 Rev. G Issue Date: February 1996
PALCE610 Family
I
I
I
2
23
VCC
I/O1
PALCE610 Family
Lattice Semiconductor
CLK1
1
24
2-375
ORDERING INFORMATION Commercial Products
Programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of:
FUNCTIONAL DESCRIPTION
The PALCE610 is a general purpose programmable logic device. It has 16 independently-configurable macrocells. Each macrocell can be configured as either combinatorial or registered. The registers can be D, T, J-K, or S-R type flip-flops. The device has 4 dedicated input pins and 2 clock pins. Each clock pin controls 8 of the 16 macrocells. The programming matrix implements a programmable AND logic array which drives a fixed OR logic array. Buffers for device inputs have complementary outputs to provide user-programmable input polarity. Unused input pins should be tied to VCC or ground. The array uses our electrically erasable technology. An unprogrammed bit is disconnected and a programmed bit is connected. Product terms with all bits unprogrammed assume the logical-HIGH state and product terms with both the TRUE and Complement bits programmed assume the logical-LOW state. The programmable functions in the PALCE610 are automatically configured from the user's design specifications, which can be in a number of formats. The design specification is processed by development software to verify the design and create a programming file. This file, once downloaded to the programmer, configures the design according to the user's desired function.
asynchronous configuration, the clock input is controlled by the product term. The output is always enabled. In The D and T configurations, feedback can be either from Q or the output pin. This allows D and T configurations to be either outputs or I/O. In the J-K and S-R configurations, feedback is only from Q; therefore, J-K and S-R configurations are strictly outputs.
PAL
CE
610 H -15 P C
D Flip-Flop
All 8 product terms are available to the OR gate. The D input polarity is controlled by an exclusive-OR gate. For the D flip-flop, the output level is the D-input level at the rising edge of the clock. D 0 0 1 1 Qn 0 1 0 1 Qn+1 0 0 1 1
FAMILY TYPE PAL = Programmable Array Logic TECHNOLOGY CE = CMOS Electrically Erasable DEVICE NUMBER 610 = 600 Gates POWER H = Half Power (90 mA ICC) SPEED -15 = 15 ns tPD -25 = 25 ns tPD
OPERATING CONDITIONS C = Commercial (0C to +75C) PACKAGE TYPE P = 24-Pin 300 mil Plastic SKINNYDIP (PD3024) J = 28-Pin Plastic Leaded Chip Carrier (PL 028)
T Flip-Flop
All 8 product terms are available to the OR gate. The T input polarity is controlled by an exclusive-OR gate. For the T register, the output level toggles when the T input is HIGH and remains the same when the T input is LOW. T Qn 0 1 0 1 Qn+1 0 1 1 0
Macrocell Configurations
Valid Combinations PALCE610H-15 PC, JC PALCE610H-25 Valid Combinations Valid Combinations lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations, and to check on newly released combinations.
0 0 1 1
The PALCE610 macrocell can be configured as either combinatorial or registered. Both the combinatorial and registered configurations have output polarity control. The register can be configured as a D, T, J-K, or S-R type flip-flop. Figure 1 shows the possible configurations. Each macrocell can select as its clock either the corresponding clock pin or the CLK/OE product term. If the clock pin is selected, the output enable is controlled by the CLK/OE product term. If the CLK/OE product term is selected, the output is always enabled.
J-K Flip-Flop
The 8 product terms are divided between the J and K inputs. N product terms go to the J input and 8-N product terms go to the K input, where N can range from 0 to 8. Both the J and K inputs to the flip-flop have polarity control via exclusive-OR gates. The J-K flip-flop operation is shown below. J 0 0 0 0 1 1 1 1 K 0 0 1 1 0 0 1 1 Qn 0 1 0 1 0 1 0 1 Qn+1 0 1 0 0 1 1 1 0
Combinatorial I/O
All 8 product terms are available to the OR gate. The output-enable function is performed by the CLK/OE product term.
Registered Configurations
There are 4 flip-flop types available: D, T, J-K and S-R. The registers can be configured as synchronous or asynchronous. In the synchronous configuration, the clock is controlled by the clock input pin. The output enable is controlled by the product term function. In the
2-376
PALCE610H-15/25 (Com'l)
PALCE610 Family
2-377
S-R Flip-Flop
The 8 product terms are divided between the S and R inputs. N product terms go to the S input and 8-N product terms go to the R input, where N can range from 0 to 8. Both the S and R inputs to the flip-flop have polarity control via exclusive-OR gates. The S-R flip-flop operation is shown below.
S 0 0 0 0 1 1 VCC CLK 1 0 1 0 VCC CLK 1 0 1 0 1 R 0 0 1 1 0 0 1 Qn 0 1 0 1 0 1 Not Allowed Qn+1 0 1 0 0 1 1
Security Bit
After programming and verification, a PALCE610 design can be secured by programming the security bit. Once programmed, this bit defeats readback of the internal programmed pattern by a device programmer, securing proprietary designs from competitors. However, programming and verification are also defeated by the security bit. The bit can only be erased in conjunction with the array during the erase cycle. Preload is not affected by the security bit.
Technology
The PALCE610 is manufactured using our advanced Electrically Erasable (EE) CMOS process. This technology uses an EE cell to replace the fuse link in bipolar parts, and allows Lattice to offer lower-power parts of high complexity. In addition, since the EE cells can be erased and reprogrammed, these devices can be 100% factory tested before being shipped to the customer. Inputs and outputs are designed to be compatible with TTL devices. This technology provides strong input clamp diodes, output slew-rate control, and a grounded substrate for clear switching.
Combinatorial
Asynchronous Reset
All flip-flops have an asynchronous-reset product-term input. When the product term is true, the flip-flop will reset to a logic LOW, regardless of the clock and data inputs.
TQ AR
DQ AR
Power-Up Reset
All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the PALCE610 depend on whether they are selected as registered or combinatorial. If registered is selected, the output will be LOW. If combinatorial is selected, the output will be a function of the logic. The VCC rise must be monotonic and the reset delay time is 1000 ns maximum.
Programming and Erasing
The PALCE610 can be programmed on standard logic programmers. It also may be erased to reset a previously configured device back to its virgin state. Bulk erase is automatically performed by the programming hardware. No special erase operation is required.
1 0
1 0
CMOS Compatibility
The PALCE610 has CMOS-compatible outputs. The output voltage (VOH) is 3.85 V at -2.0 mA.
Register Preload
T Register
VCC CLK 1 0 1 0 VCC CLK 1 0
D Register
1 0
The register on the PALCE610 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery.
N JQ 8-N K AR
N SQ 8-N R AR
J-K Register
S-R Register
12950G-4
Figure 1. Macrocell Configurations 2-378 PALCE610 Family PALCE610 Family 2-379
PALCE610 LOGIC DIAGRAM DIP (PLCC) Pinouts
40
CLK1 INPUT
1 (2) 2 (3) (4) 24 VCC (1, 28)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . -55C to +125C
0
23 (27)
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . 0C to +75C Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
INPUT I/O 1
80
Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . -0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0C to +75C) . . . . . . . . . . . . . . . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
I/O 9 3
Macrocell
AR OE/CLK 89 9
Macrocell
AR OE/CLK
22 (26)
NODE 1
NODE 16
90 I/O 10 4
(5)
10
Macrocell
AR OE/CLK 99 19
Macrocell
AR OE/CLK
21 (25)
I/O 2
NODE 2
NODE 15
100 20 I/O 11 5
(6)
Macrocell
AR OE/CLK 109 29
Macrocell
AR OE/CLK
20 (24)
I/O 3
NODE 3
NODE 14
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified (Note 2)
Parameter Symbol VOH VOL Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Leakage Current Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Supply Current Test Conditions VIN = VIH or VIL VCC = Min VIN = VIH or VIL VCC = Min IOH = -4.0 mA IOH = -2.0 mA IOL = 8.0 mA IOL = 4.0 mA 2.0 0.8 10 -10 10 -10 -30 -150 90 Min 2.4 3.84 0.5 0.45 Max Unit V V V V V V A A A A mA mA
110 I/O 12 6
(7)
30
Macrocell
NODE 4 AR OE/CLK 119 39
Macrocell
AR OE/CLK
19 (23)
I/O 4
NODE 13
I/O 13 7
120
40
(8)
Macrocell
AR OE/CLK 129 49
Macrocell
AR OE/CLK
18 (22)
I/O 5
VIH VIL IIH
NODE 5
NODE 12
Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VIN = 5.25 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VIN = 0 V, Outputs Open (IOUT = 0 mA) VCC = Max
I/O 14 8
130 50
(9)
Macrocell
AR OE/CLK 139 59
Macrocell
AR OE/CLK
17 (21)
I/O 6
NODE 6
NODE 11
IIL IOZH
I/O 15 9
(10)
140
60
Macrocell
AR OE/CLK 149 69
Macrocell
AR OE/CLK
16 (20)
I/O 7
IOZL ISC ICC
NODE 7
NODE 10
150 I/O 16 10
(12)
70
Macrocell
AR OE/CLK
Macrocell
159 79 AR OE/CLK
15 (18)
I/O 8
NODE 8
NODE 9
Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
INPUT
11 (13)
14 (17)
INPUT CLK2
GND 12
(14, 15)
0
8
16
24
32
39
0
8
16
24
32
39
13 (16)
40
12950G-5
2-380
PALCE610 Family
PALCE610H-15/25 (Com'l)
2-381
CAPACITANCE (Note 1)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VIN = 2.0 V VOUT = 2.0 V VCC = 5.0 V TA = +25C f = 1 MHz Typ 8 8 pF Unit
SWITCHING WAVEFORMS
Input or Feedback tS Input or Feedback VT tPD Combinatorial Output VT
12950G-6
VT tH VT
Clock Registered Output
Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
tCO VT
12950G-7
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter Symbol tPD tS tH tCO tWL tWH fMAX -15 Parameter Description Input or Feedback to Combinatorial Output Setup Time from Input or Feedback to Clock Hold Time Clock to Output Clock Width Maximum Frequency (Note 3) LOW HIGH External Feedback Internal Feedback (fCNT) No Feedback 1/(tS + tCO) 1/(tS + tCF) (Note 5) 1/(tWH + tWL) 6 6 50 76.1 83.3 15 15 15 10 15 5 5 15 6 6 50 61.6 83.3 10 10 28.6 29.4 50 8 12 27 15 25 12 0 8 10 10 37 40 50 25 25 25 Min Max 15 15 0 12 Min -25 Max 25 Unit ns ns ns ns ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns MHz MHz MHz Input Asserting Asynchronous Reset Product-Term Clock Clock
Combinatorial Output
Registered Output
Input tWH tER VT Output tWL
12950G-8
VT tEA VOH - 0.5V VOL + 0.5V VT
12950G-9
Clock Width
Input to Output Disable/Enable
Input or Feedback tSA tWHA VT tWLA
12950G-10
VT tHA VT tCOA
tEA tER tAR tARW tARR tSA tHA tCOA tWLA tWHA fMAXA
Input to Output Enable Using Product Term Control Input to Output Disable Using Product Term Control Asynchronous Reset to Registered Output Asynchronous Reset Width Asynchronous Reset Recovery Time Setup Time from Input or Feedback to Clock (Note 4) Hold Time (Note 4) Clock to Output (Note 4) Clock Width Maximum Frequency (Notes 3 and 4) LOW (Note 4) HIGH (Note 4) External Feedback 1/(tSA + tCOA) Internal Feedback (fCNT) No Feedback 1/(tWLA + tWHA)
Product-Term Clock
Registered Output Registered Output Using Product-Term Clock
VT
12950G-11
Clock Width Using Product-Term Clock
tARW VT tAR
Notes: 2. See Switching Test Circuit for test conditions. 3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 4. These parameters are measured using the asynchronous product-term clock. 5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS.
Registered Output
VT tARR
Clock Asynchronous Reset
VT
12950G-12
Notes:
1. VT = 1.5 V 2. Input pulse amplitude 0 V to 3.0 V 3. Input rise and fall times 2 ns-5 ns typical.
2-382
PALCE610H-15/25 (Com'l)
PALCE610 Family
2-383
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Must be Steady May Change from H to L May Change from L to H Don't Care, Any Change Permitted Does Not Apply OUTPUTS Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is HighImpedance "Off" State
KS000010-PAL
ENDURANCE
Symbol tDR Parameter Description Pattern Data Retention Time Test Conditions Max Storage Temperature Max Operating Temperature N Reprogramming Cycles Normal Programming Conditions Min 10 20 100 Unit Years Years Cycles
INPUT/OUTPUT EQUIVALENT SCHEMATICS
VCC
ESD Program/Verify Protection Circuitry
Typical Input
SWITCHING TEST CIRCUIT
5V VCC S1
R1 Output R2 Test Point Preload Circuitry Feedback Input
CL
Typical Output
12950G-13
12950G-14
Commercial Specification tPD, tCO tEA tER S1 Closed Z H: Open Z L: Closed H Z: Open L Z: Closed 35 pF 5 pF 855 340 CL R1 R2
Measured Output Value 1.5 V 1.5 V H Z: VOH - 0.5 V L Z: VOL + 0.5 V
2-384
PALCE610 Family
PALCE610 Family
2-385
Power-Up Reset
The power-up reset feature ensures that all flip-flops will be reset to LOW after the device has been powered up. This feature is valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and wide range of ways VCC can rise to
Parameter Symbol tPR tS tWL
its steady state, two conditions are required to insure a valid power-up reset. These conditions are:
s The VCC rise must be monotonic. s Following reset, the clock input must not be driven
TYPICAL THERMAL CHARACTERISTICS
Measured at 25C ambient. These parameters are not tested.
Parameter Symbol jc ja jma Parameter Description Thermal impedance, junction to case Thermal impedance, junction to ambient Thermal impedance, junction to ambient with air flow 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air Typ SKINNYDIP PLCC 21 72 64 60 55 49 20 57 47 44 40 36 Unit C/W C/W C/W C/W C/W C/W
from LOW to HIGH until all applicable input and feedback setup times are met.
Parameter Description Power-up Reset Time Input or Feedback Setup Time Clock Width LOW
Max 1000
Unit ns
See Switching Characteristics
4V Power
VCC
Plastic jc Considerations The data listed for plastic jc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the jc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment.
tPR
Registered Output
tS
Clock
tWL
12950G-15
Power-Up Reset Waveform
2-386
PALCE610 Family
PALCE610 Family
2-387

▲Up To Search▲

Price & Availability of PALCE600

	To Download PALCE600 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .